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Rev Log message Author Age Path
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)
olivier.girard 4512d 05h /
148 Update donation pictures' format. olivier.girard 4553d 03h /
147 Add donation buttons olivier.girard 4553d 14h /
146 Update ChangeLog olivier.girard 4562d 05h /
145 Add Dhrystone and CoreMark benchmarks to the simulation environment. olivier.girard 4562d 05h /
144 Update ChangeLog olivier.girard 4583d 05h /
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4583d 05h /
142 Beautify the linker script examples. olivier.girard 4583d 05h /
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 4587d 04h /
140 Update ChangeLog olivier.girard 4599d 06h /
139 Add some SVN ignore patterns olivier.girard 4599d 14h /
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4599d 15h /
137 Update ChangeLog olivier.girard 4631d 04h /
136 Update all FPGA projects with the latest core version. olivier.girard 4631d 05h /
135 Update documentation to reflect the ASIC implementation options. olivier.girard 4631d 05h /
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.
olivier.girard 4631d 05h /
133 Add support for new CPU version. olivier.girard 4631d 05h /
132 Update FPGA examples with the POP.B bug fix olivier.girard 4644d 05h /
131 Update ChangeLog olivier.girard 4652d 04h /
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 4652d 04h /

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