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Subversion Repositories openmsp430

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Rev	Log message	Author	Age	Path
41	Update bitstream & SVN ignore patterns.	olivier.girard	5445d 06h	/
40	Minor updates.	olivier.girard	5445d 06h	/
39	Update FPGA projects with new openMSP430 core.	olivier.girard	5445d 06h	/
38	Remove old core version.	olivier.girard	5445d 07h	/
37		olivier.girard	5445d 07h	/
36	Remove old core version.	olivier.girard	5445d 08h	/
35	Update documentation to reflect the latest Verilog changes.	olivier.girard	5445d 08h	/
34	To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix.	olivier.girard	5445d 09h	/
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5445d 10h	/
32	Minor update to the HTML documentation + add some SVN ignore properties to the Altera FPGA project simulation directory.	olivier.girard	5447d 06h	/
31	Update documentation (new Altera FPGA project + diverse minor updates)	olivier.girard	5447d 07h	/
30	Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution).	olivier.girard	5447d 07h	/
29	Add Altera Cyclone II FPGA project example.	olivier.girard	5447d 08h	/
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5455d 15h	/
27	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5455d 15h	/
26	Xilinx implementation example: - update the project directory structure. - make a local copy of the openMSP430 core to make the project self contained.	olivier.girard	5455d 16h	/
25	FPGA Setup: Created some BAT files for WINDOWS users.	olivier.girard	5545d 13h	/
24	FPGA Setup: Created some BAT files for WINDOWS users.	olivier.girard	5545d 13h	/
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5566d 11h	/
22	Updated some links in the HTML documentation.	olivier.girard	5579d 09h	/

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[/] - Rev 41

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