OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] - Rev 45

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
45 Temporar documentation removal because of broken SVN update. olivier.girard 5375d 12h /
44 Update documentation with the "Integration and Connectivity" section. olivier.girard 5375d 12h /
43 Re-add documentation (earlier pdf was broken). olivier.girard 5399d 12h /
42 olivier.girard 5399d 12h /
41 Update bitstream & SVN ignore patterns. olivier.girard 5399d 12h /
40 Minor updates. olivier.girard 5399d 12h /
39 Update FPGA projects with new openMSP430 core. olivier.girard 5399d 12h /
38 Remove old core version. olivier.girard 5399d 13h /
37 olivier.girard 5399d 13h /
36 Remove old core version. olivier.girard 5399d 13h /
35 Update documentation to reflect the latest Verilog changes. olivier.girard 5399d 14h /
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5399d 15h /
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5399d 16h /
32 Minor update to the HTML documentation + add some SVN ignore properties to the Altera FPGA project simulation directory. olivier.girard 5401d 12h /
31 Update documentation (new Altera FPGA project + diverse minor updates) olivier.girard 5401d 12h /
30 Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution). olivier.girard 5401d 13h /
29 Add Altera Cyclone II FPGA project example. olivier.girard 5401d 14h /
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5409d 21h /
27 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5409d 21h /
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5409d 21h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.