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Rev Log message Author Age Path
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5361d 20h /
53 Fixed the following combinatorial timing loop:
1- irq_detect (omsp_frontend)
2- decode (omsp_frontend)
3- dbg_swbrk (omsp_dbg)
4- halt_flag_set (omsp_dbg)
6- dbg_halt_cmd (omsp_dbg)
7- irq_detect (omsp_frontend)

Without this fix, problem could occur whenever an IRQ request arrives during a software breakpoint instruction fetch.		 olivier.girard 5361d 20h /
52 Re-add pdf documentation. olivier.girard 5366d 16h /
51 Re-add open-office documentation. olivier.girard 5366d 16h /
50 Re-add html documentation. olivier.girard 5366d 16h /
49 Temporar documentation removal because of broken SVN update. olivier.girard 5366d 16h /
48 Re-add html documentation. olivier.girard 5366d 16h /
47 Temporar documentation removal because of broken SVN update. olivier.girard 5366d 16h /
46 Re-add html documentation. olivier.girard 5366d 16h /
45 Temporar documentation removal because of broken SVN update. olivier.girard 5366d 16h /
44 Update documentation with the "Integration and Connectivity" section. olivier.girard 5366d 17h /
43 Re-add documentation (earlier pdf was broken). olivier.girard 5390d 16h /
42 olivier.girard 5390d 16h /
41 Update bitstream & SVN ignore patterns. olivier.girard 5390d 16h /
40 Minor updates. olivier.girard 5390d 17h /
39 Update FPGA projects with new openMSP430 core. olivier.girard 5390d 17h /
38 Remove old core version. olivier.girard 5390d 17h /
37 olivier.girard 5390d 17h /
36 Remove old core version. olivier.girard 5390d 18h /
35 Update documentation to reflect the latest Verilog changes. olivier.girard 5390d 18h /

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