OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 151

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
151 OR1200 rel3 (added some files that were not checked-in earlier) marcus.erlandsson 5257d 18h /
150 removed Linux directories marcus.erlandsson 5258d 03h /
149 Initial commit of the GCC test suite jeremybennett 5259d 04h /
148 The port of newlib for OpenRISC. This version just works with Or1ksim. There is code for a UART based version, but that needs some more work.

This allows GCC to be tested using Or1ksim.		 jeremybennett 5259d 19h /
147 Integration of Or1ksim as a GDB simulator. jeremybennett 5259d 20h /
146 Restructured Or1k implementation. Now works without frame pointer, using unified code approach. jeremybennett 5259d 20h /
145 Fixed bug in data structure initialization. jeremybennett 5259d 20h /
144 Missing file to fix bug 1797. jeremybennett 5259d 22h /
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5259d 23h /
142 added OpenRISC version rel3 marcus.erlandsson 5260d 02h /
141 added OpenRISC version rel3 marcus.erlandsson 5260d 02h /
140 Changes to ORPMon, probably broke flash loading, improved TFTP julius 5261d 02h /
139 added rel3 info in tags-directory, to avoid misunderstanding marcus.erlandsson 5262d 01h /
138 fixed check-in mistake (remove additional directory level) marcus.erlandsson 5262d 01h /
137 Release-2 of the OR1200 processor, latest version is always located in trunk-directory marcus.erlandsson 5262d 02h /
136 Adding crossbild script, updating MOF install script to use or1ksim-0.4.0 julius 5262d 23h /
135 Tagging the 0.4.0 stable release of Or1ksim jeremybennett 5268d 03h /
134 Updates for stable release 0.4.0 jeremybennett 5268d 03h /
133 Patches for floating point support jeremybennett 5272d 00h /
132 This fixes files formatted with DOS line endings (something that should be sorted out outside SVN). jeremybennett 5272d 00h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.