OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 456

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4990d 10h /
455 Updated to support threads. Does require thread debugging enabled in uClibc. jeremybennett 4994d 12h /
454 Updated to incorporate pthreads for Linux tool chain. jeremybennett 4996d 13h /
453 Updates to support constructor/destructor initialization for uClibc. jeremybennett 4997d 00h /
452 Update to define __UCLIBC__ when using the uClibc tool chain. jeremybennett 4997d 08h /
451 More tidying up. jeremybennett 5001d 04h /
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 5001d 08h /
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 5003d 05h /
448 Changed or32 to openrisc as Linux architecture name. jeremybennett 5003d 15h /
447 Updates to register order. jeremybennett 5004d 09h /
446 gdb-7.2 gdbserver updates. julius 5005d 03h /
445 gdbserver update to use kernel port ptrace register definitions. julius 5006d 00h /
444 Changes to ABI handling of varargs. jeremybennett 5006d 09h /
443 Work in progress on more efficient Ethernet. jeremybennett 5006d 12h /
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 5007d 03h /
441 Changes for gdbserver. jeremybennett 5007d 09h /
440 Updated documentation to describe new Ethernet usage. jeremybennett 5008d 04h /
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 5010d 08h /
438 Fix to newlib header and library locations. jeremybennett 5013d 09h /
437 Or1ksim - ethernet peripheral update, working much better. julius 5015d 23h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.