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Rev Log message Author Age Path
458 or1ksim testsuite updates julius 4947d 23h /
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4956d 13h /
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4956d 15h /
455 Updated to support threads. Does require thread debugging enabled in uClibc. jeremybennett 4960d 17h /
454 Updated to incorporate pthreads for Linux tool chain. jeremybennett 4962d 18h /
453 Updates to support constructor/destructor initialization for uClibc. jeremybennett 4963d 05h /
452 Update to define __UCLIBC__ when using the uClibc tool chain. jeremybennett 4963d 13h /
451 More tidying up. jeremybennett 4967d 09h /
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 4967d 13h /
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 4969d 10h /
448 Changed or32 to openrisc as Linux architecture name. jeremybennett 4969d 20h /
447 Updates to register order. jeremybennett 4970d 14h /
446 gdb-7.2 gdbserver updates. julius 4971d 08h /
445 gdbserver update to use kernel port ptrace register definitions. julius 4972d 05h /
444 Changes to ABI handling of varargs. jeremybennett 4972d 14h /
443 Work in progress on more efficient Ethernet. jeremybennett 4972d 17h /
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 4973d 08h /
441 Changes for gdbserver. jeremybennett 4973d 14h /
440 Updated documentation to describe new Ethernet usage. jeremybennett 4974d 09h /
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 4976d 13h /

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