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Rev	Log message	Author	Age	Path
59	Toolchain install script gcc patch change and gdb configure change	julius	5379d 11h	/
58	ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up	julius	5382d 10h	/
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5387d 14h	/
56	adding generic pll model to orpsoc	julius	5395d 16h	/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5398d 07h	/
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5408d 14h	/
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5426d 14h	/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5427d 10h	/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5441d 13h	/
50	Adding or32_funcs.S	julius	5441d 17h	/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5460d 07h	/
48	Adds an initialization to keep GCC happy in jp1_ll_read_jp1.	jeremybennett	5460d 09h	/
47	debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions	julius	5469d 17h	/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5475d 18h	/
45	Orpsoc eth test fix and script error message update	julius	5482d 17h	/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5511d 17h	/
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5535d 14h	/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5551d 11h	/
41	Update to or1k top	julius	5554d 12h	/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5555d 18h	/

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Subversion Repositories openrisc

[/] - Rev 59

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