OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 637

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
637 porint parallel port(gpio) management task filepang 4841d 16h /
636 porting serial port management task, interrupt hander filepang 4841d 16h /
635 Patch for http://bugzilla.opencores.org/show_bug.cgi?id=69.

* config/or32/linux-elf.h <TARGET_OS_CPP_BUILTINS>: Defined, based
on LINUX_TARGET_OS_CPP_BUILTINS copied from linux.h.		 jeremybennett 4842d 20h /
634 orpsoc: atlys: autoregenerate coregen cores

Instead of keeping binary .ngc files of the coregen
generated cores, use coregen to generate them from the .xco
and .cgp file		 stekern 4844d 03h /
633 orpsoc: add Digilent Atlys spartan6 board README

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>		 stekern 4844d 03h /
632 orpsoc: add Digilent Atlys spartan6 board sw include file

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>		 stekern 4844d 03h /
631 orpsoc: add Digilent Atlys spartan6 board testbench

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>		 stekern 4844d 03h /
630 orpsoc: add Digilent Atlys spartan6 board backend

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>		 stekern 4844d 03h /
629 orpsoc: add Digilent Atlys spartan6 board or1ksim configuration

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>		 stekern 4844d 03h /
628 orpsoc: add Digilent Atlys spartan6 board Makefiles

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>		 stekern 4844d 03h /
627 orpsoc: add Digilent Atlys spartan6 board rtl

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>		 stekern 4844d 03h /
626 Fix to support GCC 4.6 by disabling -Werror. jeremybennett 4852d 18h /
625 Fixed configuration to work with GCC 4.6, added -Werror to avoid GCC 4.6 warning as a temporary fix. Added pic.cfg to EXTRA_DIST. Made tests build with SILENT_RULES if available. jeremybennett 4852d 19h /
624 add missing delay slot instruction
vPortDisableInterrupts
vPortEnableInterrupts		 filepang 4853d 23h /
623 cleanup source code
Demo/OpenRISC_SIM_GCC/arch/support.h
Demo/OpenRISC_SIM_GCC/arch/interrupts.h
Demo/OpenRISC_SIM_GCC/arch/link.ld

add gpio driver

add gpio base address definition		 filepang 4854d 15h /
622 update uart driver for support multiple uart cores
from http://opencores.org/ocsvn/openrisc/openrisc/trunk/orpsocv2/sw/drivers/uart		 filepang 4854d 17h /
621 update sim.cfg for newer version of Or1ksim.
remove unused files.
cleanup source code.

insert non-local jump(setjmp) in xPortStartScheduler. now xPortStartScheduler() will
be returned by xPortEndScheduler().		 filepang 4856d 09h /
620 remove unused file
cleanup makefile
update uart_init(), disable interrupt before initialize.		 jeremybennett 4856d 22h /
619 ORPSoC OR1200 fix and regression test for bug 51.

signed-off Julius Baxter
reviewed by Stefan Kristiansson		 julius 4865d 10h /
618 Remove unused parameter Tp olof 4865d 17h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.