OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 667

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
667 Corrected ITLB/DTLB values according to the arch spec.
This partially fixes bug #58
olof 4644d 19h /
666 FreeRTOSV6.1.1
minimal set of standard demo task is working
filepang 4645d 22h /
665 FreeRTOSV6.1.1
fix context save/restore stack size bug
remove unnecessary line
filepang 4645d 22h /
664 FreeRTOSV6.1.1
modify processor abstraction layer.
now,all tasks are running in supervisor mode
filepang 4645d 22h /
663 Fix compatibility problems with GCC 4.6.1. Fix a bug with hardware floating point in GCC. jeremybennett 4649d 17h /
662 minor corrections to clean simulation files paknick 4665d 19h /
661 added makefile for icarus simulation paknick 4665d 19h /
660 updated makefiles for simulation with altera ordb2a-ep4ce22 paknick 4665d 22h /
659 Fixed longjmp hal implementation skrzyp 4668d 02h /
658 example configuration uses RAM startup skrzyp 4686d 00h /
657 test generation fixed skrzyp 4686d 01h /
656 orpsoc: cfi_ctrl software driver fix to allow compilation when it's not used julius 4690d 16h /
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4690d 16h /
654 added eCos-3.0 port skrzyp 4691d 21h /
653 Make gdb link to or1ksim's libsim last, so wrapper works yannv 4698d 23h /
652 Fix make compile.tcl for actel backend yannv 4698d 23h /
651 ORPSoC: The ability to use a free/gimped version of Modelsim was restricted to
the reference build's scripts. This patch adds support for it to the
scripts for the board builds as well.

Signed-off-by: Julius Baxter <julius at opencores.org>
acked-by: Stefan Kristiansson <stefan.kristiansson at saunalahti.fi>
julius 4703d 18h /
650 ORPSoC: documentation update to fix explanation of Xilinx environment setup, add section for Atlys board, various cleanups julius 4704d 16h /
649 porting some of standard demo tasks

fix serial port(UART) interrupt handler
filepang 4720d 21h /
648 docs: OR1K architecture now labeled as revision 0 in draft spec julius 4723d 17h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.