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Rev Log message Author Age Path
696 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4516d 10h /
695 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4516d 10h /
694 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4516d 10h /
693 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4516d 11h /
692 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4516d 11h /
691 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4516d 11h /
690 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4516d 11h /
689 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4516d 11h /
688 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4516d 11h /
687 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4516d 11h /
686 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4516d 11h /
685 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4516d 11h /
684 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4516d 11h /
683 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4516d 12h /
682 Fixed error message in Makefile skrzyp 4516d 19h /
681 Updated to reflect latest scripts and creation of separate directory for development versions. jeremybennett 4517d 09h /
680 New directory structure for development tool chain tracking upstream mainline. jeremybennett 4517d 09h /
679 Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 olof 4517d 11h /
678 added credits skrzyp 4517d 14h /
677 atlys: add 2-clock synchronizer chain for ddr2_calib_done

The signal ddr2_calib_done signal comes from the ddr2 clock domain,
while wb_req is treating it as if it came from wb_clk domain. As a
result the timing analysis tool assumed a worst case scenario of 5ns
between the two domains and the results were miserable.

While we can argue that this is a multi-cycle path, the fact is that
ddr2_calib_done feeds into multiple logic sinks and can potentially
cause meta-stability issue in the design. The solution is to add a
2-clock meta-stability filter to address both the timing problems and
the meta-stability concern.

Signed-off-by: Jason Zheng <jxzheng@gmail.com>
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Acked-by: Olof Kindgren <olof.kindgren@orsoc.se>		 stekern 4525d 13h /

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