OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] - Rev 271

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
271 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5305d 12h /
270 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5305d 12h /
269 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5305d 12h /
268 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5305d 12h /
267 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5305d 12h /
266 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5305d 13h /
265 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5305d 13h /
264 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5305d 13h /
263 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5305d 13h /
262 Baseline port of GCC 4.5.1 for OpenRISC 1000. jeremybennett 5305d 13h /
261 Linux patch update - all ioremap calls now default with cache inhibit julius 5307d 02h /
260 Fixed `define in FPU that didnt need to be there julius 5307d 03h /
259 Fixing or1200_defines FPU module selection defines - They are no longer needed julius 5308d 22h /
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5308d 23h /
257 Changed or1200 supplementary manual from referring or or1200v2 to be just for the or1200 in general julius 5309d 09h /
256 Linux patch update - disabled SCET driver by default julius 5310d 04h /
255 Linux patch update with USB host data cache issue solved, file formatting fixed julius 5312d 06h /
254 Update of Linux patch with USB driver, rename of its or1ksim config file julius 5312d 23h /
253 No need to define PROTOTYPES, now DWARF 2 debugging is the default. jeremybennett 5313d 10h /
252 Changes to use source and line info when DWARF debug data is available. jeremybennett 5313d 10h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.