| Rev |
Log message |
Author |
Age |
Path |
| 494 |
Change to ensure handles ctrl-C correctly with empty line. |
jeremybennett |
5015d 15h |
/ |
| 493 |
ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. |
julius |
5017d 23h |
/ |
| 492 |
ORPSoC VPI interface for modelsim and documentation update |
julius |
5018d 21h |
/ |
| 491 |
ORPSoC or1200_monitor update. |
julius |
5019d 08h |
/ |
| 490 |
Updates to fix spurious test failures and register scheduling. |
jeremybennett |
5023d 14h |
/ |
| 489 |
ORPSoC sw cleanup. Remove warnings. |
julius |
5028d 20h |
/ |
| 488 |
ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. |
julius |
5028d 21h |
/ |
| 487 |
ORPSoC main software makefile update |
julius |
5031d 19h |
/ |
| 486 |
ORPSoC updates, mainly software, i2c driver |
julius |
5031d 19h |
/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
5035d 23h |
/ |
| 484 |
Changes to make r12 call-saved and to bring wchar tests in line. |
jeremybennett |
5036d 22h |
/ |
| 483 |
Updated with new opcodes to generate random numbers and to identify us as Or1ksim. |
jeremybennett |
5039d 00h |
/ |
| 482 |
Don't hardcode tool versions in help text |
olof |
5040d 12h |
/ |
| 481 |
OR1200 Update. RTL and spec. |
julius |
5052d 06h |
/ |
| 480 |
ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. |
julius |
5053d 04h |
/ |
| 479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
5054d 03h |
/ |
| 478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
5055d 19h |
/ |
| 477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
5056d 03h |
/ |
| 476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
5056d 20h |
/ |
| 475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
5056d 23h |
/ |
