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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

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Rev Log message Author Age Path
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 5005d 04h /
495 ORPSoC adding more accessor functions to Micron SDRAM model. julius 5005d 05h /
494 Change to ensure handles ctrl-C correctly with empty line. jeremybennett 5015d 22h /
493 ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. julius 5018d 06h /
492 ORPSoC VPI interface for modelsim and documentation update julius 5019d 04h /
491 ORPSoC or1200_monitor update. julius 5019d 15h /
490 Updates to fix spurious test failures and register scheduling. jeremybennett 5023d 21h /
489 ORPSoC sw cleanup. Remove warnings. julius 5029d 04h /
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 5029d 04h /
487 ORPSoC main software makefile update julius 5032d 02h /
486 ORPSoC updates, mainly software, i2c driver julius 5032d 02h /
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 5036d 07h /
484 Changes to make r12 call-saved and to bring wchar tests in line. jeremybennett 5037d 05h /
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 5039d 07h /
482 Don't hardcode tool versions in help text olof 5040d 19h /
481 OR1200 Update. RTL and spec. julius 5052d 13h /
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 5053d 11h /
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 5054d 11h /
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 5056d 02h /
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 5056d 10h /

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