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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

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Rev Log message Author Age Path
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5350d 23h /
56 adding generic pll model to orpsoc julius 5359d 01h /
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5361d 15h /
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5371d 23h /
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5389d 23h /
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5390d 19h /
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5404d 22h /
50 Adding or32_funcs.S julius 5405d 02h /
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5423d 15h /
48 Adds an initialization to keep GCC happy in jp1_ll_read_jp1. jeremybennett 5423d 18h /
47 debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions julius 5433d 02h /
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5439d 03h /
45 Orpsoc eth test fix and script error message update julius 5446d 02h /
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5475d 02h /
43 Couple of fixes to ORPSoC, new linux patch version in toolchain script julius 5498d 23h /
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5514d 20h /
41 Update to or1k top julius 5517d 21h /
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5519d 03h /
39 Adding OR debug proxy a makefile tweak for uClibc and toolchain install script update julius 5523d 03h /
38 Adding binutils, gcc, uClibc patched source and patches julius 5533d 02h /

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