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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

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Rev Log message Author Age Path
80 Add missing configuration files to SVN. jeremybennett 5289d 22h /
79 Fixed retry loop in or_debug_proxy, hopefully more stable when physically resetting the board julius 5301d 23h /
78 Fixed typo in Silos workaround script rherveille 5302d 18h /
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour		 rherveille 5302d 18h /
76 Added: +libext+.v
Added: +incdir+.		 rherveille 5303d 18h /
75 Fixed toolchain script's cygwin ncurses check julius 5308d 20h /
74 Toolchain script fix for ncurses header checking julius 5326d 23h /
73 toolchain script error fix julius 5327d 00h /
72 Toolchain install script: or1ksim location changed, few tweaks julius 5329d 21h /
71 ORPSoC board builds, adding readmes julius 5346d 04h /
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5350d 08h /
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5350d 09h /
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5353d 01h /
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5353d 04h /
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5373d 02h /
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5377d 08h /
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5380d 03h /
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5390d 00h /
62 This material is part of the separate website downloads directory. jeremybennett 5401d 03h /
61 The build directory should not be part of the SVN configuration. jeremybennett 5401d 04h /

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