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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

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82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.		 jeremybennett 5685d 20h /
81 Directory no longer used. jeremybennett 5685d 21h /
80 Add missing configuration files to SVN. jeremybennett 5686d 00h /
79 Fixed retry loop in or_debug_proxy, hopefully more stable when physically resetting the board julius 5698d 01h /
78 Fixed typo in Silos workaround script rherveille 5698d 20h /
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour		 rherveille 5698d 20h /
76 Added: +libext+.v
Added: +incdir+.		 rherveille 5699d 20h /
75 Fixed toolchain script's cygwin ncurses check julius 5704d 22h /
74 Toolchain script fix for ncurses header checking julius 5723d 01h /
73 toolchain script error fix julius 5723d 02h /
72 Toolchain install script: or1ksim location changed, few tweaks julius 5725d 23h /
71 ORPSoC board builds, adding readmes julius 5742d 06h /
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5746d 10h /
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5746d 11h /
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5749d 03h /
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5749d 06h /
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5769d 04h /
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5773d 10h /
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5776d 05h /
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5786d 02h /

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