OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] - Rev 334

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
334 Record changes to the documentation and option handling. jeremybennett 5344d 20h /
333 Fix the default option (to use -mhard-mul). Update the documentation for
OpenRISC.
jeremybennett 5344d 21h /
332 Provide support for nested functions. Tidy up board specification.

* config/or32/or32-protos.c <or32_trampoline_code_size>: Added.
* config/or32/or32.c <OR32_MOVHI, OR32_ORI, OR32_LWZ, OR32_JR>:
New macros added.
(or32_emit_mode, or32_emit_binary, or32_force_binary)
(or32_trampoline_code_size, or32_trampoline_init): Created.
(or32_output_bf): Tabbing fixed.
<TARGET_TRAMPOLINE_INIT>: Definition added.
* config/or32/or32.h <STATIC_CHAIN_REGNUM>: Uses R11.
<TRAMPOLINE_SIZE>: redefined.
<TRAMPOLINE_ENVIRONMENT>: Added definition.
jeremybennett 5345d 20h /
331 Updated for GDB 7.2 and GCC 4.5.1 (which needs target-libgcc). jeremybennett 5346d 04h /
330 Baseline port of GDB 7.2 for OpenRISC 1000 jeremybennett 5346d 15h /
329 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5346d 16h /
328 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5346d 16h /
327 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5346d 16h /
326 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5346d 16h /
325 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5346d 16h /
324 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5346d 16h /
323 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5346d 16h /
322 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5346d 16h /
321 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5346d 16h /
320 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5346d 16h /
319 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5346d 16h /
318 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5346d 16h /
317 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5346d 16h /
316 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5346d 16h /
315 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5346d 16h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.