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Rev Log message Author Age Path
366 Version 1.0 toolchain script commit julius 5179d 15h /
365 Linux-2.6.34 patch update with updated USB ohs900 host julius 5182d 09h /
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.
julius 5191d 08h /
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.
julius 5191d 18h /
362 ORPSoCv2 verilator building working again. Board build fixes to follow julius 5193d 03h /
361 OPRSoCv2 - adding things left out in last check-in julius 5193d 08h /
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5193d 08h /
359 Removing duplicate OR1200 spec from docs/ path, original in or1200/doc should be used instead, also moving Japanese OR1200 spec to or1200/doc julius 5193d 15h /
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.
julius 5193d 17h /
357 Tidied up commenting. jeremybennett 5193d 18h /
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests
julius 5194d 02h /
355 Adding CoreMark to ORPmon, updated Dhrystone test output julius 5194d 10h /
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.
julius 5195d 08h /
353 OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.

ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""

or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)

ORPmon play around, various changes to low level files.
julius 5195d 10h /
352 OR1200 RTL DC sensitivity list fix julius 5196d 08h /
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5196d 08h /
350 Adding new OR1200 processor to ORPSoCv2 julius 5196d 12h /
349 ORPSoCv2 update with new software and makefile update julius 5196d 12h /
348 First stage of ORPSoCv2 update - more to come julius 5196d 13h /
347 Tagging the 0.5.0rc1 candidate release of Or1ksim. jeremybennett 5196d 14h /

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