OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] - Rev 459

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
459 Add option to bld-all.sh to explicitly set control load of make, and fix typos. julius 5166d 09h /
458 or1ksim testsuite updates julius 5167d 08h /
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 5175d 22h /
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 5175d 23h /
455 Updated to support threads. Does require thread debugging enabled in uClibc. jeremybennett 5180d 01h /
454 Updated to incorporate pthreads for Linux tool chain. jeremybennett 5182d 03h /
453 Updates to support constructor/destructor initialization for uClibc. jeremybennett 5182d 14h /
452 Update to define __UCLIBC__ when using the uClibc tool chain. jeremybennett 5182d 22h /
451 More tidying up. jeremybennett 5186d 18h /
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 5186d 22h /
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 5188d 18h /
448 Changed or32 to openrisc as Linux architecture name. jeremybennett 5189d 04h /
447 Updates to register order. jeremybennett 5189d 22h /
446 gdb-7.2 gdbserver updates. julius 5190d 17h /
445 gdbserver update to use kernel port ptrace register definitions. julius 5191d 14h /
444 Changes to ABI handling of varargs. jeremybennett 5191d 22h /
443 Work in progress on more efficient Ethernet. jeremybennett 5192d 02h /
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 5192d 16h /
441 Changes for gdbserver. jeremybennett 5192d 23h /
440 Updated documentation to describe new Ethernet usage. jeremybennett 5193d 18h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.