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Rev Log message Author Age Path
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5559d 09h /
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5564d 13h /
56 adding generic pll model to orpsoc julius 5572d 15h /
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5575d 05h /
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5585d 12h /
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5603d 13h /
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5604d 09h /
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5618d 11h /
50 Adding or32_funcs.S julius 5618d 15h /
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5637d 05h /
48 Adds an initialization to keep GCC happy in jp1_ll_read_jp1. jeremybennett 5637d 08h /
47 debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions julius 5646d 16h /
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5652d 16h /
45 Orpsoc eth test fix and script error message update julius 5659d 16h /
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5688d 16h /
43 Couple of fixes to ORPSoC, new linux patch version in toolchain script julius 5712d 13h /
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5728d 10h /
41 Update to or1k top julius 5731d 11h /
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5732d 16h /
39 Adding OR debug proxy a makefile tweak for uClibc and toolchain install script update julius 5736d 17h /

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