URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] - Rev 82

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
82	Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check". Incorporate Mark Jarvis's fixes for Mac OS X.	jeremybennett	5208d 01h	/
81	Directory no longer used.	jeremybennett	5208d 02h	/
80	Add missing configuration files to SVN.	jeremybennett	5208d 05h	/
79	Fixed retry loop in or_debug_proxy, hopefully more stable when physically resetting the board	julius	5220d 06h	/
78	Fixed typo in Silos workaround script	rherveille	5221d 01h	/
77	Added support for Silvaco's Silos simulator Added workaround for Silos's exit code behaviour	rherveille	5221d 01h	/
76	Added: +libext+.v Added: +incdir+.	rherveille	5222d 01h	/
75	Fixed toolchain script's cygwin ncurses check	julius	5227d 03h	/
74	Toolchain script fix for ncurses header checking	julius	5245d 06h	/
73	toolchain script error fix	julius	5245d 07h	/
72	Toolchain install script: or1ksim location changed, few tweaks	julius	5248d 04h	/
71	ORPSoC board builds, adding readmes	julius	5264d 11h	/
70	ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\!	julius	5268d 15h	/
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5268d 16h	/
68	Fixed up a couple of Makefile things in ORPSoCv2	julius	5271d 08h	/
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5271d 11h	/
66	Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software.	julius	5291d 09h	/
65	ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix	julius	5295d 15h	/
64	Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile.	julius	5298d 10h	/
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5308d 07h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories openrisc_me

[/] - Rev 82

Filtering Options