OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 1024

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1024 Mess with printf/PRINTF fixed. Ethernet test changed to support latest changes. simons 8121d 04h /
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 8121d 14h /
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8121d 17h /
1021 *** empty log message *** rherveille 8125d 19h /
1020 Fixed several bugs
Working version, tested on Bender hardware
rherveille 8125d 19h /
1019 fixed some bugs detected by Bender hardware rherveille 8125d 19h /
1018 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 8126d 02h /
1017 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 8126d 03h /
1016 64 bytes is the smallest packet size. simons 8126d 19h /
1015 Host type was not recognized. simons 8127d 05h /
1014 added _JBLEN definition for or1k ivang 8127d 18h /
1013 ORP architecture supported. simons 8127d 20h /
1012 This commit was manufactured by cvs2svn to create tag 'rel_4'. 8128d 13h /
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 8128d 13h /
1010 Import ivang 8132d 16h /
1009 Import ivang 8132d 17h /
1008 Import ivang 8132d 17h /
1007 Import ivang 8132d 17h /
1006 Import ivang 8132d 17h /
1005 Import ivang 8132d 18h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.