OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 1186

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1186 Added support for rams with byte write access. simons 7682d 15h /
1185 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7689d 08h /
1184 Scan signals mess fixed. simons 7689d 08h /
1183 OpenRISC port of gdb-5.3 straightforwardly derived from gdb-5.0 sfurman 7693d 23h /
1182 This commit was manufactured by cvs2svn to create tag 'VER_5_3'. 7694d 02h /
1181 Initial import of unmodified gdb-5.3 source on vendor branch sfurman 7694d 02h /
1180 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7697d 11h /
1179 BIST interface added for Artisan memory instances. simons 7697d 11h /
1178 avoid another immu exception that should not happen phoenix 7726d 22h /
1177 more informative output phoenix 7728d 05h /
1176 Added comments. damonb 7728d 20h /
1175 Added three missing wire declarations. No functional changes. lampret 7728d 23h /
1174 fix for immu exceptions that never should have happened phoenix 7730d 00h /
1173 Added QMEM. lampret 7731d 08h /
1172 Added embedded memory QMEM. lampret 7731d 09h /
1171 Added embedded memory QMEM. lampret 7731d 09h /
1170 Added support for l.addc instruction. csanchez 7738d 04h /
1169 Added support for l.addc instruction. csanchez 7738d 05h /
1168 Added explicit alignment expressions. csanchez 7743d 15h /
1167 Corrected offset of TSS field within task_struct. csanchez 7743d 15h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.