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Rev Log message Author Age Path
1614 CI should not be set in dMMU translation tables or one gets different behaviour with dMMU on or off in case data cache is enabled. care should be taken for addresses higher than 0x7fff_ffff where the situation is just reversed. (since or1200 does not cache upper half of address space if there is no dMMU) phoenix 6759d 00h /
1613 change default phoenix 6764d 09h /
1612 major optimizations for or32 target phoenix 6764d 10h /
1611 This commit was manufactured by cvs2svn to create tag 'stable_0_2_0_rc2'. 6767d 11h /
1610 Update ChangeLog nogj 6767d 11h /
1609 0.2.0-rc2 release nogj 6767d 12h /
1608 Avoid scheduleing too many jobs, potentially underflowing the scheduler stack nogj 6768d 06h /
1607 Don't drop cycles from the scheduler nogj 6768d 06h /
1606 fix uninitialized reads phoenix 6768d 11h /
1605 Execute l.ff1 instruction nogj 6775d 06h /
1604 Fix dumphex/dumpverilog to not do unaligned memory access nogj 6775d 06h /
1603 Accept EM_OPENRISC as a valid machine nogj 6776d 10h /
1602 Corrected description of l.sfXXui (arch manual had a wrong description compared to behavior implemented in or1ksim/gcc/or1200). Removed Atomicity chapter. lampret 6777d 08h /
1601 fixed description of l.sfXXXi lampret 6777d 09h /
1600 Corrected mistake in pin assignation due to typo error in RC203 manual jcastillo 6785d 10h /
1599 Corrected Syn Script to add MMU memories jcastillo 6785d 16h /
1598 Handle ethernet addresses as an address and not as an int nogj 6787d 08h /
1597 Fix parsing the destination register nogj 6787d 08h /
1596 Fix handling of eof in the sim cli nogj 6787d 08h /
1595 Add default immu/dmmu page size nogj 6787d 08h /

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