URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 1631

Rev	Log message	Author	Age	Path
1631	First Import	jcastillo	7277d 12h	/
1630	* empty log message *	jcastillo	7277d 12h	/
1629	First Import of uClinux for RC20x board	jcastillo	7277d 13h	/
1628	First Import of uClinux for RC20x board	jcastillo	7277d 13h	/
1627	First Import of RC20x uClinux	jcastillo	7277d 13h	/
1626	First Import of uClinux for RC20x board	jcastillo	7277d 13h	/
1625	First Import of uClinux for RC20x board	jcastillo	7277d 13h	/
1624	First Import of uClinux for RC20x board	jcastillo	7277d 14h	/
1623	First Import of uClinux for RC20x board	jcastillo	7277d 14h	/
1622	First Import of uClinux for RC20x board	jcastillo	7277d 14h	/
1621	First Impot	jcastillo	7277d 15h	/
1620	Added SMC91C111 LAN Chip Interruption to work with uClinux	jcastillo	7282d 11h	/
1619	Fixed types in function declaration	jcastillo	7282d 16h	/
1618	Import of or32 sepcific part of binutils port updated by Balint and Nog	phoenix	7282d 22h	/
1617	* empty log message *	phoenix	7282d 22h	/
1616	Import of or32 sepcific part of binutils port updated by Balint and Nog	phoenix	7282d 22h	/
1615	* empty log message *	phoenix	7282d 23h	/
1614	CI should not be set in dMMU translation tables or one gets different behaviour with dMMU on or off in case data cache is enabled. care should be taken for addresses higher than 0x7fff_ffff where the situation is just reversed. (since or1200 does not cache upper half of address space if there is no dMMU)	phoenix	7292d 23h	/
1613	change default	phoenix	7298d 08h	/
1612	major optimizations for or32 target	phoenix	7298d 09h	/