URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 167

Rev	Log message	Author	Age	Path
167	- SPR values corrected - testbenches now work - lot of optimizations, use --disable-debugmod for optimal performance - some tick timer bugs fixed	markom	8357d 23h	/
166	Fixed RAM's oen bug. Cache bypass under development.	lampret	8375d 10h	/
165	Added variable ack of WB transfers (see NODELAY_WBx).	lampret	8375d 10h	/
164	* empty log message *	lampret	8377d 12h	/
163	Forgot files.f file.	lampret	8377d 12h	/
162	Benches (under development).	lampret	8377d 12h	/
161	Development version of RTL. Libraries are missing.	lampret	8377d 12h	/
160	simulation script	lampret	8377d 13h	/
159	synthesis scripts	lampret	8377d 13h	/
158	Initial RTEMS import	chris	8387d 03h	/
157	Update	simons	8394d 06h	/
156	File moved to opcode.	simons	8394d 06h	/
155	Update	simons	8394d 06h	/
154	Updated for new runtime environment	chris	8400d 06h	/
153	Writes to SPR_PC are now enabled	chris	8400d 06h	/
152	Breakpoint exceptions from single step are not printed now.	chris	8400d 06h	/
151	Typo in the previous commit. Sorry.	chris	8400d 06h	/
150	Fixed some single stepping issues	chris	8400d 06h	/
149	Fixed bug where disassemble command caused a segmentation fault	chris	8401d 09h	/
148	Replace single stepping patch that got overwritten	chris	8401d 09h	/