URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 195

Rev	Log message	Author	Age	Path
195	New test added.	simons	8483d 03h	/
194	Fixed a bug for little endian architectures. Could cause a hang of gdb under some circumstances.	chris	8483d 10h	/
193	Declared RISCOP.RESET to be volatile so that -O2 optimization would not optimize away the correct behavior by trying to be too clever.	chris	8483d 11h	/
192	Removed GlobalMode reference causing problems for --disable-debugmod option.	chris	8483d 20h	/
191	Added UART jitter var to sim config	chris	8484d 16h	/
190	Added jitter initialization	chris	8484d 16h	/
189	fixed mode handling for tick facility	chris	8484d 16h	/
188	fixed PIC interrupt controller	chris	8484d 16h	/
187	minor change to clear pending exception	chris	8484d 16h	/
186	major change to UART structure	chris	8484d 16h	/
185	major change to UART code	chris	8484d 16h	/
184	modified decode for trace debugging	chris	8484d 16h	/
183	changed special case for PICSR	chris	8484d 16h	/
182	updated exception handling procedures	chris	8484d 16h	/
181	Added trace/stall commands	chris	8484d 16h	/
180	Updated debug.	lampret	8484d 22h	/
179	Sim run script	lampret	8504d 15h	/
178	Some test code	lampret	8504d 15h	/
177	Improved wb_sram model	lampret	8504d 15h	/
176	IC enable/disable.	lampret	8504d 15h	/