OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 204

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
204 Added function prototypes to stop gcc from complaining erez 8560d 06h /
203 Updated from xess branch. lampret 8561d 19h /
202 changed configure.in and acconfig.h to check for long long
reran autoheader & autoconf
erez 8567d 03h /
201 readfunc() and writefunc() now use unsigned long values instead of unsigned char. erez 8567d 03h /
200 Initial import simons 8570d 10h /
199 Initial import simons 8570d 11h /
198 Moved from testbench.old simons 8572d 22h /
197 This is not used any more. simons 8572d 22h /
196 Configuration SPRs added. simons 8572d 23h /
195 New test added. simons 8572d 23h /
194 Fixed a bug for little endian architectures. Could cause a hang of
gdb under some circumstances.
chris 8573d 07h /
193 Declared RISCOP.RESET to be volatile so that -O2 optimization would
not optimize away the correct behavior by trying to be too clever.
chris 8573d 07h /
192 Removed GlobalMode reference causing problems for --disable-debugmod
option.
chris 8573d 16h /
191 Added UART jitter var to sim config chris 8574d 12h /
190 Added jitter initialization chris 8574d 12h /
189 fixed mode handling for tick facility chris 8574d 13h /
188 fixed PIC interrupt controller chris 8574d 13h /
187 minor change to clear pending exception chris 8574d 13h /
186 major change to UART structure chris 8574d 13h /
185 major change to UART code chris 8574d 13h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.