OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 217

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
217 Fixed some synthesis warnings. Configured with caches and MMUs. lampret 8430d 05h /
216 No longer needed. lampret 8435d 16h /
215 MP3 version. lampret 8435d 16h /
214 Removed redundant "long long" checks erez 8445d 18h /
213 Added test5 for DMA erez 8445d 19h /
212 Added DMA erez 8445d 19h /
211 Added check for "long long" erez 8445d 19h /
210 Updated debug. More cleanup. Added MAC. lampret 8449d 00h /
209 Update debug. lampret 8451d 05h /
208 Initial checkin with working port to or1k chris 8452d 17h /
207 Several major changes to allow gdb to work with an Or1k implementation
that does not need a writeable PC. This version will use the breakpoint
vector and install a new vector into the EPC register, and then single
step out of the breakpoint exception. The breakpoint exception vector
must include only 2 commands: l.rfe and l.nop. Anything else and this
gdb version will fail w/ or1ksim.
chris 8452d 21h /
206 Several modifications to support gdb in a new exception style mode.
This new version works with gdb, and does not require the simulator
to implement a writeable PC.
chris 8452d 21h /
205 Adding debug capabilities. Half done. lampret 8457d 00h /
204 Added function prototypes to stop gcc from complaining erez 8459d 16h /
203 Updated from xess branch. lampret 8461d 05h /
202 changed configure.in and acconfig.h to check for long long
reran autoheader & autoconf
erez 8466d 13h /
201 readfunc() and writefunc() now use unsigned long values instead of unsigned char. erez 8466d 13h /
200 Initial import simons 8469d 20h /
199 Initial import simons 8469d 21h /
198 Moved from testbench.old simons 8472d 08h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.