URL https://opencores.org/ocsvn/or1k/or1k/trunk

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Rev	Log message	Author	Age	Path
22	More modifications related to or16.	lampret	8836d 05h	/
21	More modifications related to or16.	cmchen	8836d 05h	/
20	or1k renamed to or32.	lampret	8836d 18h	/
19	Added or16, or1k renamed to or32.	lampret	8836d 19h	/
18	or16 added, or1k renamed to or32.	lampret	8836d 19h	/
17	Re-generated.	jrydberg	8859d 15h	/
16	Add support for systems without readline. To use GNU readline library, use the `--enable-readline' option to the configure script.	jrydberg	8859d 15h	/
15	Initial revision.	jrydberg	8896d 06h	/
14	First import.	lampret	8896d 08h	/
13	Rebuild of the generated files.	jrydberg	8897d 11h	/
12	Added information to the section about how to configure and compile the package.	jrydberg	8897d 11h	/
11	Rebuild from configure.in.	jrydberg	8897d 11h	/
10	Support for both architectures. Specify architecture with the --target option.	jrydberg	8897d 11h	/
9	Added support for OpenRISC 100 and DLX.	jrydberg	8897d 11h	/
8	Initial revision.	jrydberg	8897d 11h	/
7	Major update of the enviorment. Now uses autoconf and automake. The simulator uses readline aswell to get input from the user. A number of new files added, some modified. The libc directory is now called support.	jrydberg	8897d 11h	/
6	Just a regular update with exception of cache simulation. MMU simulation still under development.	lampret	8898d 05h	/
5	Data and instruction cache simulation added.	lampret	8898d 05h	/
4	no message	lampret	8948d 09h	/
3	This commit was generated by cvs2svn to compensate for changes in r2, which included commits to RCS files with non-trunk default branches.	cvs	9023d 23h	/

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