URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 355

Rev	Log message	Author	Age	Path
355	uart VAPI model improved; changes to MC and eth.	markom	8409d 11h	/
354	Fixed width of du_except.	lampret	8409d 21h	/
353	Cashes disabled.	simons	8410d 08h	/
352	OR1200_REGISTERED_OUTPUTS can now be enabled.	lampret	8411d 11h	/
351	Fixed some l.trap typos.	lampret	8411d 12h	/
350	For GDB changed single stepping and disabled trap exception.	lampret	8411d 14h	/
349	Some bugs regarding cache simulation fixed.	simons	8413d 02h	/
348	Added instructions on how to build configure.	ivang	8414d 10h	/
347	Added CRC32 calculation to Ethernet	erez	8415d 07h	/
346	Improved Ethernet simulation	erez	8415d 09h	/
345	Added check for net/ethernet.h (needed by ethernet simulator)	erez	8415d 09h	/
344	added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model	markom	8415d 11h	/
343	Small touches to test programs	erez	8415d 13h	/
342	added exception vectors to support and modified section names	markom	8416d 10h	/
341	added VAPI for uart; uart 16550 support, some bugs fixed	markom	8416d 12h	/
340	Added hpint vector	lampret	8416d 12h	/
339	Added setpc test	lampret	8416d 12h	/
338	Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)	lampret	8416d 12h	/
337	Fixed tick timer interrupt reporting by using TTCR[IP] bit.	lampret	8416d 12h	/
336	VAPI works	markom	8417d 08h	/