OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 406

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
406 Renamed ethernet's RX_BD_ADR to RX_BD_NUM erez 8554d 07h /
405 Stepping trough l.jal and l.jalr fixed. simons 8555d 09h /
404 is_delayed() is used outside this file. simons 8555d 09h /
403 Prompt changed because ddd requires (gdb). simons 8555d 09h /
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8555d 13h /
401 *** empty log message *** simons 8558d 23h /
400 force_dslot_fetch does not work - allways zero. simons 8558d 23h /
399 Trap insn couses break after exits ex_insn. simons 8558d 23h /
398 added register field defines ivang 8561d 05h /
397 removed or16 architecture markom 8561d 06h /
396 added missing file markom 8561d 08h /
395 removed obsolete dependency and history from cpu section markom 8561d 10h /
394 dependency joined with dependstats; history moved to sim section markom 8561d 11h /
393 messages: exception on many places changed to abort markom 8561d 11h /
392 This commit was manufactured by cvs2svn to create tag 'stable'. 8561d 19h /
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8561d 19h /
390 Changed instantiation name of VS RAMs. lampret 8561d 21h /
389 Changed default delay for load and store in superscalar cpu. lampret 8561d 21h /
388 Added comments for cpu section. lampret 8561d 21h /
387 Now FPGA and ASIC target are separate. lampret 8561d 22h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.