OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 486

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
486 Updated documentation in default sim.cfg erez 8404d 01h /
485 gdb.h moved to debug dir; except.ld renamed to default.ld markom 8404d 02h /
484 Changed to support execution from various addresses. simons 8404d 14h /
483 Implemented some GPIO tests erez 8404d 15h /
482 profiling uses l.jr instead of obsolete l.jalr markom 8404d 19h /
481 -f bug fixed markom 8404d 19h /
480 RTL_SIM define added for shorter simulation runtime. simons 8404d 19h /
479 connection with gdb repaired; temp_except_delay removed; lot of except and debug code cleaned; sys 203 causes stall under gdb; non-sim memory area log bug fixed markom 8404d 19h /
478 Started adding acv_gpio testbench erez 8404d 19h /
477 Improved multi-id vapi logs (i.e. GPIO) erez 8404d 19h /
476 Fixed warnings. ivang 8404d 20h /
475 l.jalr r9 is not used any more. simons 8404d 21h /
474 Updated building instructions. or1.h not used anymore. ivang 8404d 21h /
473 Added test flag templates. ivang 8405d 01h /
472 Removed MC initialization. Must be done in except_mc.S ivang 8405d 01h /
471 Removed MC initialization. Must be done in except_mc.S ivang 8405d 01h /
470 Added test flag templates. ivang 8405d 01h /
469 Added test flag templates ivang 8405d 01h /
468 Removed MC initialization. Must be done in except_mc.S ivang 8405d 01h /
467 Fixed some typos. ivang 8405d 01h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.