OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 499

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
499 Made testbench/support/int.c more usable and changed acv_gpio test to use it erez 8316d 17h /
498 Fixed data type bug in l_mac() that caused incorrect calculation of MACHI. Possible that l_msb has the same bug. lampret 8328d 02h /
497 Fixed encoding of the following insns: l.mac,l.msb,l.maci,l.mtspr,l.mfspr lampret 8328d 03h /
496 Added generation of instruction set reference document. ivang 8328d 14h /
495 added missing enddevice command in GPIO section markom 8328d 14h /
494 trace.h removed; removed absolete trace_fd code - use exe_log instead markom 8328d 14h /
493 --enable-opt switch added to testbench configure markom 8328d 17h /
492 uart THRE interrupt immedialty after write to IER markom 8328d 17h /
491 pc command fixed markom 8329d 13h /
490 clkcycle parsing problem fixed markom 8329d 13h /
489 blank page at beginning and at the end of the isa doc. markom 8329d 13h /
488 *** empty log message *** ivang 8329d 18h /
487 Lectored english descriptions by Bob Gardner-Medwin. Thanks Bob! markom 8329d 18h /
486 Updated documentation in default sim.cfg erez 8329d 19h /
485 gdb.h moved to debug dir; except.ld renamed to default.ld markom 8329d 20h /
484 Changed to support execution from various addresses. simons 8330d 08h /
483 Implemented some GPIO tests erez 8330d 09h /
482 profiling uses l.jr instead of obsolete l.jalr markom 8330d 13h /
481 -f bug fixed markom 8330d 13h /
480 RTL_SIM define added for shorter simulation runtime. simons 8330d 13h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.