URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 641

Rev	Log message	Author	Age	Path
641	Modified logging of SPR accesses. Logging only explicit instruction accesses.	ivang	8181d 07h	/
640	Merge profiler and mprofiler with sim.	ivang	8181d 09h	/
639	MMU cache inhibit bit test added.	simons	8183d 23h	/
638	TLBTR CI bit is now working properly.	simons	8184d 00h	/
637	Updated file names.	lampret	8184d 01h	/
636	Fixed combinational loops.	lampret	8184d 01h	/
635	Fixed Makefile bug.	ivang	8184d 03h	/
634	configure.in : fixed to build start/Makefile start.S : l.jalr r9 -> l.jr r9 Added missing files.	ivang	8185d 04h	/
633	Bug fix in command line parser.	ivang	8185d 05h	/
632	profiler and mprofiler merged into sim.	ivang	8186d 00h	/
631	Real cache access is simulated now.	simons	8186d 23h	/
630	some bug fixes in store buffer analysis	markom	8187d 08h	/
629	typo fixed	markom	8187d 11h	/
628	This commit was manufactured by cvs2svn to create tag 'pre-GNU-merge'.		8187d 12h	/
627	or32 restored	markom	8187d 12h	/
626	store buffer added	markom	8187d 12h	/
625	Bus error bug fixed. Cache routines added.	simons	8188d 04h	/
624	Added logging of writes/read to/from SPR registers.	ivang	8188d 04h	/
623	update based on recent changes; arithmetic instructions does not modify carry yet	markom	8188d 06h	/
622	Cache test works on hardware.	simons	8188d 09h	/