URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] - Rev 798

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Rev	Log message	Author	Age	Path
798	Hardware scroll added. This possible due to the fact that crt is wrapping around 512k boundary.	simons	8285d 23h	/
797	Changed hardcoded address for fake MC to use a define.	lampret	8286d 00h	/
796	Removed unused ports wb_clki and wb_rst_i	lampret	8286d 00h	/
795	Added a directive to ignore signed division variables that are only used in simulation.	lampret	8286d 04h	/
794	Added again just recently removed full_case directive	lampret	8286d 04h	/
793	Added synthesis off/on for timescale.v included file.	lampret	8286d 04h	/
792	Fixed port names that changed.	lampret	8286d 04h	/
791	Fixed some ports in instnatiations that were removed from the modules	lampret	8286d 04h	/
790	Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives	lampret	8286d 05h	/
789	Added response from memory controller (addr 0x60000000)	lampret	8286d 05h	/
788	Some of the warnings fixed.	lampret	8286d 06h	/
787	Added romfs.tgz	lampret	8287d 00h	/
786	Moved UCF constraint file to the backend directory.	lampret	8287d 00h	/
785	Added XSV specific documentation.	lampret	8287d 00h	/
784	Added soem missing files.	lampret	8287d 00h	/
783	Added sim directory and sub files/dirs.	lampret	8287d 00h	/
782	Added the old SW directory. It needs to be updated for the new ORP environment and test cases moved to sw directory.	lampret	8287d 00h	/
781	Added design compiler scripts. However these are not ready for use yet .... They need to be updated for the ORP sources and ORP sources need to be updated as well.	lampret	8287d 01h	/
780	Added libraries.	lampret	8287d 01h	/
779	Added bench directory	lampret	8287d 01h	/

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[/] - Rev 798

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