OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 879

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
879 Initial version of OpenRISC Custom Unit Compiler added markom 8179d 04h /
878 first release of atabug rherveille 8180d 22h /
877 ata beta release rherveille 8180d 22h /
876 Beta release of ATA simulation rherveille 8180d 22h /
875 libgcc is moved here to avoid the mess with the folders. simons 8181d 11h /
874 Command for displaying trace buffer added. simons 8189d 05h /
873 There is a problem with CRC generation, it has to be fixed in the future. simons 8200d 10h /
872 Touch screen test added. simons 8204d 10h /
871 Generic flip-flop based memory macro for register file. lampret 8205d 05h /
870 Added defines for enabling generic FF based memory macro for register file. lampret 8205d 05h /
869 Added generic flip-flop based memory macro instantiation. lampret 8205d 05h /
868 help added for mprofiler and profiler commands markom 8208d 15h /
867 ifdefs changed to ifs, to exclude ethernet_i header file markom 8210d 15h /
866 after make headers markom 8214d 10h /
865 true flase bug fixed markom 8216d 05h /
864 Change the order of biulding tools. simons 8217d 04h /
863 Some additional changes for RAM version. simons 8218d 03h /
862 Support for compressed kernel image added. simons 8218d 03h /
861 This commit was manufactured by cvs2svn to create tag 'tn_m001'. 8220d 23h /
860 Added delayr and delayw variable initialization (default value 1) ivang 8220d 23h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.