OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 962

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8141d 14h /
961 uart16550 RTL files renamed/added/removed. lampret 8141d 14h /
960 Directory cleanup. lampret 8141d 14h /
959 Fixed size of generic flash/sram to exactly 2MB lampret 8142d 13h /
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8142d 13h /
957 Flash at 0x04000000 RAM at 0x00000000. Only MMU test works. simons 8143d 00h /
956 Changed to work with or32-uclinux tool chain. Everything works except keyboard test. simons 8143d 04h /
955 typos and grammar fixed markom 8144d 05h /
954 some debugging code cleanup markom 8144d 08h /
953 burst detection for bytes & halfwords added markom 8144d 09h /
952 Added or1200_monitor top. lampret 8144d 14h /
951 Updated file names lampret 8144d 14h /
950 Removed nop.log. Added general.log and lookup.log. In the middle of moving test cases. lampret 8144d 14h /
949 Added more WISHBONE protocol checks. Removed nop.log. Added general.log and lookup.log. lampret 8144d 14h /
948 Fixed reference name lampret 8144d 14h /
947 rty_i are unused - tied to zero. lampret 8144d 14h /
946 Added SRAM_GENERIC lampret 8144d 14h /
945 Changed logic when FLASH_GENERIC_REGISTERED lampret 8144d 14h /
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8144d 14h /
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 8144d 14h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.