URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 976

Rev	Log message	Author	Age	Path
976	Added store buffer	lampret	8142d 07h	/
975	First checkin	lampret	8142d 07h	/
974	Enabled what works on or1ksim and disabled other tests.	lampret	8142d 09h	/
973	generated cuc top scheduler builds without syntax errors; not tested yet	markom	8144d 14h	/
972	Interrupt suorces fixed.	simons	8144d 14h	/
971	Now even keyboard test passes.	simons	8144d 17h	/
970	Testbench is now running on ORP architecture platform.	simons	8145d 05h	/
969	Checking in except directory.	lampret	8145d 21h	/
968	Checking in utils directory.	lampret	8145d 21h	/
967	Checking in mul directory.	lampret	8145d 21h	/
966	Checking in cbasic directory.	lampret	8145d 21h	/
965	Checking in basic directory.	lampret	8145d 21h	/
964	Checking in support directory.	lampret	8145d 21h	/
963	This commit was manufactured by cvs2svn to create tag 'rel_2'.		8145d 21h	/
962	Fixed Xilinx trace buffer address. REported by Taylor Su.	lampret	8145d 21h	/
961	uart16550 RTL files renamed/added/removed.	lampret	8145d 21h	/
960	Directory cleanup.	lampret	8145d 21h	/
959	Fixed size of generic flash/sram to exactly 2MB	lampret	8146d 21h	/
958	Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.	lampret	8146d 21h	/
957	Flash at 0x04000000 RAM at 0x00000000. Only MMU test works.	simons	8147d 07h	/