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Rev Log message Author Age Path
989 c++ is making problems so, for now, it is excluded. simons 8136d 06h /
988 ORP architecture supported. simons 8136d 22h /
987 ORP architecture supported. simons 8137d 05h /
986 outputs out of function are not registered anymore markom 8137d 06h /
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8137d 17h /
984 Disable SB until it is tested lampret 8137d 17h /
983 First checkin lampret 8137d 19h /
982 Moved to sim/bin lampret 8137d 19h /
981 First checkin. lampret 8137d 19h /
980 Removed sim.tcl that shouldn't be here. lampret 8137d 19h /
979 Removed old test case binaries. lampret 8137d 19h /
978 Added variable delay for SRAM. lampret 8137d 19h /
977 Added store buffer. lampret 8137d 19h /
976 Added store buffer lampret 8137d 19h /
975 First checkin lampret 8137d 19h /
974 Enabled what works on or1ksim and disabled other tests. lampret 8137d 22h /
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 8140d 02h /
972 Interrupt suorces fixed. simons 8140d 02h /
971 Now even keyboard test passes. simons 8140d 05h /
970 Testbench is now running on ORP architecture platform. simons 8140d 18h /

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