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Rev Log message Author Age Path
989 c++ is making problems so, for now, it is excluded. simons 7966d 20h /
988 ORP architecture supported. simons 7967d 12h /
987 ORP architecture supported. simons 7967d 19h /
986 outputs out of function are not registered anymore markom 7967d 20h /
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 7968d 07h /
984 Disable SB until it is tested lampret 7968d 07h /
983 First checkin lampret 7968d 09h /
982 Moved to sim/bin lampret 7968d 09h /
981 First checkin. lampret 7968d 09h /
980 Removed sim.tcl that shouldn't be here. lampret 7968d 09h /
979 Removed old test case binaries. lampret 7968d 09h /
978 Added variable delay for SRAM. lampret 7968d 09h /
977 Added store buffer. lampret 7968d 09h /
976 Added store buffer lampret 7968d 09h /
975 First checkin lampret 7968d 09h /
974 Enabled what works on or1ksim and disabled other tests. lampret 7968d 11h /
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 7970d 16h /
972 Interrupt suorces fixed. simons 7970d 16h /
971 Now even keyboard test passes. simons 7970d 19h /
970 Testbench is now running on ORP architecture platform. simons 7971d 08h /

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