URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 994

Rev	Log message	Author	Age	Path
994	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.	lampret	8493d 10h	/
993	Fixed IMMU bug.	lampret	8493d 10h	/
992	A bug when cache enabled and bus error comes fixed.	simons	8493d 19h	/
991	Different memory controller.	simons	8493d 19h	/
990	Test is now complete.	simons	8493d 19h	/
989	c++ is making problems so, for now, it is excluded.	simons	8495d 03h	/
988	ORP architecture supported.	simons	8495d 19h	/
987	ORP architecture supported.	simons	8496d 02h	/
986	outputs out of function are not registered anymore	markom	8496d 02h	/
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	8496d 14h	/
984	Disable SB until it is tested	lampret	8496d 14h	/
983	First checkin	lampret	8496d 16h	/
982	Moved to sim/bin	lampret	8496d 16h	/
981	First checkin.	lampret	8496d 16h	/
980	Removed sim.tcl that shouldn't be here.	lampret	8496d 16h	/
979	Removed old test case binaries.	lampret	8496d 16h	/
978	Added variable delay for SRAM.	lampret	8496d 16h	/
977	Added store buffer.	lampret	8496d 16h	/
976	Added store buffer	lampret	8496d 16h	/
975	First checkin	lampret	8496d 16h	/