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Rev Log message Author Age Path
1001 fixed load/store state machine verilog generation errors markom 8121d 12h /
1000 IC/DC cache enable routines fixed. simons 8121d 12h /
999 Now every ramdisk image should have init program. simons 8121d 13h /
998 added missing fout initialization markom 8121d 15h /
997 PRINTF should be used instead of printf; command redirection repaired markom 8121d 16h /
996 some minor bugs fixed markom 8122d 15h /
995 This commit was manufactured by cvs2svn to create tag 'rel_3'. 8122d 22h /
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8122d 22h /
993 Fixed IMMU bug. lampret 8122d 22h /
992 A bug when cache enabled and bus error comes fixed. simons 8123d 07h /
991 Different memory controller. simons 8123d 08h /
990 Test is now complete. simons 8123d 08h /
989 c++ is making problems so, for now, it is excluded. simons 8124d 15h /
988 ORP architecture supported. simons 8125d 07h /
987 ORP architecture supported. simons 8125d 14h /
986 outputs out of function are not registered anymore markom 8125d 15h /
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8126d 02h /
984 Disable SB until it is tested lampret 8126d 03h /
983 First checkin lampret 8126d 05h /
982 Moved to sim/bin lampret 8126d 05h /

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