OpenCores
URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] - Rev 1193

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1193 disabled SRAM_GENERIC and added comment +
corrected 'wb_err' into 'wb_err_o'		 dries 7697d 20h /
1192 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address		 dries 7697d 21h /
1191 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address		 dries 7697d 22h /
1190 This commit was manufactured by cvs2svn to create tag 'rel_14'. 7713d 20h /
1189 This commit was manufactured by cvs2svn to create tag 'rel_13'. 7713d 20h /
1188 Added support for rams with byte write access. simons 7713d 20h /
1187 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7714d 19h /
1186 Added support for rams with byte write access. simons 7714d 19h /
1185 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7721d 12h /
1184 Scan signals mess fixed. simons 7721d 12h /
1183 OpenRISC port of gdb-5.3 straightforwardly derived from gdb-5.0 sfurman 7726d 04h /
1182 This commit was manufactured by cvs2svn to create tag 'VER_5_3'. 7726d 06h /
1181 Initial import of unmodified gdb-5.3 source on vendor branch sfurman 7726d 06h /
1180 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7729d 15h /
1179 BIST interface added for Artisan memory instances. simons 7729d 15h /
1178 avoid another immu exception that should not happen phoenix 7759d 03h /
1177 more informative output phoenix 7760d 09h /
1176 Added comments. damonb 7761d 01h /
1175 Added three missing wire declarations. No functional changes. lampret 7761d 04h /
1174 fix for immu exceptions that never should have happened phoenix 7762d 05h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.