OpenCores
URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] - Rev 1196

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1196 removed second debug/Makefile (credits: Daniel Wiklund - danwi@isy.liu.se) dries 7736d 09h /
1195 made the project file a little bit more universal dries 7736d 10h /
1194 correct all the syntax errors dries 7736d 10h /
1193 disabled SRAM_GENERIC and added comment +
corrected 'wb_err' into 'wb_err_o'
dries 7736d 10h /
1192 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address
dries 7736d 11h /
1191 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address
dries 7736d 12h /
1190 This commit was manufactured by cvs2svn to create tag 'rel_14'. 7752d 10h /
1189 This commit was manufactured by cvs2svn to create tag 'rel_13'. 7752d 10h /
1188 Added support for rams with byte write access. simons 7752d 10h /
1187 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7753d 09h /
1186 Added support for rams with byte write access. simons 7753d 09h /
1185 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7760d 02h /
1184 Scan signals mess fixed. simons 7760d 02h /
1183 OpenRISC port of gdb-5.3 straightforwardly derived from gdb-5.0 sfurman 7764d 18h /
1182 This commit was manufactured by cvs2svn to create tag 'VER_5_3'. 7764d 20h /
1181 Initial import of unmodified gdb-5.3 source on vendor branch sfurman 7764d 20h /
1180 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7768d 05h /
1179 BIST interface added for Artisan memory instances. simons 7768d 05h /
1178 avoid another immu exception that should not happen phoenix 7797d 17h /
1177 more informative output phoenix 7798d 23h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.