URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] - Rev 185

Rev	Log message	Author	Age	Path
185	major change to UART code	chris	8471d 23h	/
184	modified decode for trace debugging	chris	8471d 23h	/
183	changed special case for PICSR	chris	8471d 23h	/
182	updated exception handling procedures	chris	8471d 23h	/
181	Added trace/stall commands	chris	8471d 23h	/
180	Updated debug.	lampret	8472d 05h	/
179	Sim run script	lampret	8491d 22h	/
178	Some test code	lampret	8491d 22h	/
177	Improved wb_sram model	lampret	8491d 22h	/
176	IC enable/disable.	lampret	8491d 22h	/
175	Added new configure option --enable-impl=[default,mp3,bender], which defines IMPL_impl. It selects implementation specific environment. One should #ifdef the code that is different than default.	markom	8492d 17h	/
174	Few changes that should be done previously: - machine.h replaced by spr_defs.h - if reset label does not exist, boot from 0x0100	markom	8492d 20h	/
173	- profiler added, use e.g.: make profiler ./sim -profile -fast executable ./profiler -g [-c] (no special compiling options necessary)	markom	8494d 23h	/
172	Removing obsolete files.	lampret	8496d 02h	/
171	Added monitor.v and timescale.v	lampret	8496d 02h	/
170	Added cfg regs. Moved all defines into one defines.v file. More cleanup.	lampret	8496d 02h	/
169	Fixed memory cells. Moved monitor.h into monitor.v	lampret	8496d 02h	/
168	Major clean-up.	lampret	8499d 16h	/
167	- SPR values corrected - testbenches now work - lot of optimizations, use --disable-debugmod for optimal performance - some tick timer bugs fixed	markom	8500d 15h	/
166	Fixed RAM's oen bug. Cache bypass under development.	lampret	8518d 02h	/