OpenCores
URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] - Rev 186

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
186 major change to UART structure chris 8369d 07h /
185 major change to UART code chris 8369d 07h /
184 modified decode for trace debugging chris 8369d 07h /
183 changed special case for PICSR chris 8369d 07h /
182 updated exception handling procedures chris 8369d 07h /
181 Added trace/stall commands chris 8369d 07h /
180 Updated debug. lampret 8369d 13h /
179 Sim run script lampret 8389d 06h /
178 Some test code lampret 8389d 06h /
177 Improved wb_sram model lampret 8389d 06h /
176 IC enable/disable. lampret 8389d 06h /
175 Added new configure option --enable-impl=[default,mp3,bender],
which defines IMPL_impl.
It selects implementation specific environment. One should
#ifdef the code that is different than default.
markom 8390d 01h /
174 Few changes that should be done previously:
- machine.h replaced by spr_defs.h
- if reset label does not exist, boot from 0x0100
markom 8390d 04h /
173 - profiler added, use e.g.:
make profiler
./sim -profile -fast executable
./profiler -g [-c]

(no special compiling options necessary)
markom 8392d 08h /
172 Removing obsolete files. lampret 8393d 10h /
171 Added monitor.v and timescale.v lampret 8393d 10h /
170 Added cfg regs. Moved all defines into one defines.v file. More cleanup. lampret 8393d 10h /
169 Fixed memory cells. Moved monitor.h into monitor.v lampret 8393d 10h /
168 Major clean-up. lampret 8397d 00h /
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed
markom 8398d 00h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.