URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] - Rev 198

Rev	Log message	Author	Age	Path
198	Moved from testbench.old	simons	8471d 08h	/
197	This is not used any more.	simons	8471d 08h	/
196	Configuration SPRs added.	simons	8471d 09h	/
195	New test added.	simons	8471d 09h	/
194	Fixed a bug for little endian architectures. Could cause a hang of gdb under some circumstances.	chris	8471d 17h	/
193	Declared RISCOP.RESET to be volatile so that -O2 optimization would not optimize away the correct behavior by trying to be too clever.	chris	8471d 17h	/
192	Removed GlobalMode reference causing problems for --disable-debugmod option.	chris	8472d 02h	/
191	Added UART jitter var to sim config	chris	8472d 22h	/
190	Added jitter initialization	chris	8472d 22h	/
189	fixed mode handling for tick facility	chris	8472d 22h	/
188	fixed PIC interrupt controller	chris	8472d 22h	/
187	minor change to clear pending exception	chris	8472d 22h	/
186	major change to UART structure	chris	8472d 22h	/
185	major change to UART code	chris	8472d 22h	/
184	modified decode for trace debugging	chris	8472d 22h	/
183	changed special case for PICSR	chris	8472d 22h	/
182	updated exception handling procedures	chris	8472d 22h	/
181	Added trace/stall commands	chris	8472d 22h	/
180	Updated debug.	lampret	8473d 04h	/
179	Sim run script	lampret	8492d 21h	/