URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] - Rev 203

Rev	Log message	Author	Age	Path
203	Updated from xess branch.	lampret	8356d 08h	/
202	changed configure.in and acconfig.h to check for long long reran autoheader & autoconf	erez	8361d 16h	/
201	readfunc() and writefunc() now use unsigned long values instead of unsigned char.	erez	8361d 16h	/
200	Initial import	simons	8364d 23h	/
199	Initial import	simons	8365d 00h	/
198	Moved from testbench.old	simons	8367d 11h	/
197	This is not used any more.	simons	8367d 11h	/
196	Configuration SPRs added.	simons	8367d 11h	/
195	New test added.	simons	8367d 12h	/
194	Fixed a bug for little endian architectures. Could cause a hang of gdb under some circumstances.	chris	8367d 19h	/
193	Declared RISCOP.RESET to be volatile so that -O2 optimization would not optimize away the correct behavior by trying to be too clever.	chris	8367d 20h	/
192	Removed GlobalMode reference causing problems for --disable-debugmod option.	chris	8368d 05h	/
191	Added UART jitter var to sim config	chris	8369d 01h	/
190	Added jitter initialization	chris	8369d 01h	/
189	fixed mode handling for tick facility	chris	8369d 01h	/
188	fixed PIC interrupt controller	chris	8369d 01h	/
187	minor change to clear pending exception	chris	8369d 01h	/
186	major change to UART structure	chris	8369d 01h	/
185	major change to UART code	chris	8369d 01h	/
184	modified decode for trace debugging	chris	8369d 01h	/