OpenCores
URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] - Rev 552

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
552 Added option to read configuration from MC.
Fixed bugs in address calculation.
ivang 8346d 20h /
551 fsim runs 4 times faster than sim markom 8346d 21h /
550 deprecated GDB_ENABLED and DEBUG_ENABLED macros removed markom 8346d 22h /
549 enabled parameters removed from devices, which also have number of devices; command line --output-cfg parameter added markom 8346d 22h /
548 update of mprofiler markom 8347d 01h /
547 memory profiler added markom 8347d 03h /
546 Alignment bug fixed. simons 8347d 16h /
545 Fixed mc_read_word() bug! ivang 8347d 18h /
544 Added GPIO output for progress indication for FPGA simulation. ivang 8347d 20h /
543 Memory controller fixed. simons 8347d 22h /
542 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8347d 22h /
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8347d 23h /
540 CS number added to mem dev list. simons 8348d 01h /
539 Missing parts added. simons 8348d 02h /
538 memory width increased to 32bit; new memory test mem_test added - simple big endian test markom 8348d 02h /
537 memory cycles are calculated according to parameters from .cfg file markom 8348d 04h /
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8348d 11h /
535 stats is updated; statical single stats removed; t command output cleaned, added time output; cycles is moved to instructions; cycles now count time markom 8348d 21h /
534 Changed to work with new simulator. simons 8348d 23h /
533 profiler updated; lot of comments; bug with missaligned return call resolving fixed markom 8349d 02h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.